The Core Microarchitecture (part 5)
The Problem of Power Consumption
So, by now we should be accustomed to the idea that performance is a function of clock speed and the instructions per clock (IPC) cycle that a processor executes.
However, if performance is one side of a two-sided coin, then the other side of the coin is power consumption. What good is performance if power requirements go through the ceiling?
Increasing the Frequency
For decades, microprocessor makers were able to advance performance primarily by increasing the clock speed of CPUs. The problem was that, in order to increase performance by a little, CPU designers had to increase the power by a lot, relatively speaking.
The farsighted knew this could not go on indefinitely. In 1999, Fred Pollack, comparing power requirements and performance between processor generations, made the astute observation, “we are on the wrong side of a square law“.
However, if common sense told us that this process of increasing the frequency could not go on forever, no one seemed to know exactly when it would end either. In the event, it was the NetBurst microarchitecture, and the Pentium 4 processor, that discovered the limits of gigahertz, and the life of the NetBurst microarchitecture had to be cut short.
Today, clock speeds have progressed to the point that it will be difficult to increase them at a sustained rate in the future. Clock speeds may increase: however, not at the rate of the past. In place of gigahertz, we are to see the proliferation of CPU cores on single dies and within CPU packages.
Moving to Multiple Cores
Adding cores is actually just another way of increasing the instructions per clock (IPC) cycle that a processor is able to carry out. Remember, IPC is one of the two most important determiners of performance.
By doubling the number of cores on your CPU, in theory you double the number of instructions that a CPU is able to carry out at a time. That’s a 100% increase in performance. That’s not bad. That’s also theoretical, too.
The problem is that if you have an application that is single-theaded, and written to handle just one programming stream, all the cores in the world will do you no more good than a single core.
So it’s up to the software to extract that extra performance out of multiple computing cores. Remember, the number of instructions that a processor executes at a time (IPC) is itself a function of CPU microarchitecture design and software design.
In the past, software saw an immediate boost as the frequency of the CPU was pumped up. In the future, software shall have to be written to make the most of the hardware.
Another Formula
If performance is a function of clock speed and instructions per clock (IPC), then there’s also an equation for power consumption. It’s complicated.
Power consumption relates to dynamic capacitance, multiplied by the voltage squared, multiplied by the frequency. There, I told you it was complicated.
In order to deliver energy efficient CPUs, the designers of the Core microarchitecture had to take into account both formulas, both the one for performance and the once for power consumption. They had to balance “IPC efficiency and dynamic capacitance with the required voltage and frequency to optimize for performance and power efficiency“.