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3-core Phenoms, when they debut in the first quarter, will still not be clocked very high, and they are still experiencing delays. 8700, 8650, and 8450 triple-core Phenoms are not expected until the second quarter.

The B3 stepping is the chip revision that is supposed to correct the TLB erratum. Even the B3-stepping 3-core Phenoms will be slow. Phenom 8650 and 8450 “will have frequencies of 2.3GHz and 2.1GHz” (DIGITIMES).

The speed issue points to ongoing yield issues. This has little to do with the TLB (Translation Lookaside Buffer) erratum, which is a bug in the hardware.

Will the price/performance ratio of 3-core Phenoms cause Intel to slash prices its on its 4-core CPUs?

I don’t think so.

AMD’s 3-core CPUs are a good idea because they will allow AMD to increase its yields (by not discarding quad-core CPUs with underperforming cores). However, in order for AMD to successfully market 3-core CPUs, it will have to discount them at dual-core prices.

On a related note, while the slow speeds of AMD CPUs may have little to do with the TLB erratum, AMD is also rumored to be having TLB problems again. Problems are said to have to do with quad-core Phenoms, but what applies to quad-core Phenom should also apply to AMD quad-core servers.

According to motherboard makers, “the reason for the delay of 9700 and 9900 is because AMD has not yet been able to solve the translation lookaside buffer (TLB) erratum” (DIGITIMES).

Read more here and here.

It’s hard to build credibility yet easy to lose it.

AMD faces the specter of having worked to build credibility throughout 2003 to 2006, only to see it fade before them in 2007. A lot of credibility has “drained away in the last eight months” (p. 2).

Maybe AMD should imitate Intel for the time being until AMD gets back on its feet.

Barcelona has had a long history of problems. The chip was almost a no-show as early as CeBIT. Now AMD is at long last admitting what many in the industry have been saying. The delays of the Barcelona chip were due to yield problems.

The product manager of Opteron has now explained that problems with the complexity of Barcelona “did not allow the company to deliver proper yields”. AMD was not “yielding the volumes”. And the company was having trouble “ramping up the learning curve”.

Hindsight is always 20/20. One indication that Barcelona was having yield problems was the announcement of three-core CPUs.

A three-core CPU is not a technical feat. It’s still a good idea. Rather than throw away an entire CPU die, just disable the core that is not up-to-snuff. That way, you can still make use of the whole wafer, the whole cow, so to speak. That is, rather than cut out just the fillet and prime rib of a beast, you use the whole cow.

Management steadfastly denied that Barcelona was experiencing yield issues. The process technology was fine, they said. There was an issue of marriage between process and design, whatever that means. One thing it meant is that AMD was having yield issues.

Yield issues are not the same as the TLB (Translation-Lookaside Buffer) erratum. No, they’re different. It wasn’t until after the launch of Barcelona that AMD “also ran into this erratum”.

All processors have bugs. By the time a processor ships, however, the more serious issues are supposed to be worked out.

One analyst was worried that something is wrong with the way in which AMD tests its chips. The TLB error ought to have been caught. That may be.

However, it seems that the debugging process of server chips these days is a collaborative effort between processor and server makers. This appears to be one reason processors are sampled. To help work out the bugs.

In the future AMD intends to get “chips into the hands of OEMs faster to allow for more testing and debugging”.

AMD will sample the new Barcelona chip, sans TLB bug, to server makers in Q1. From AMD server partners in Q2 of ‘08 “expect to see products”.

Read more here.

Barcelona is the codename for the new quad-core Opterons from AMD. At a recent conference call, AMD confessed that the first stage of the ramp of Barcelona had been “slower than anticipated”.

The current period hopes to be better. AMD managed to ship tens of thousands of quad-core processors in the previous period. In the current period, AMD hopes to ship hundreds of thousands. These hundreds of thousands of processors shall include desktop quad-cores as well as server CPUs this time around.

Yields not the Issue

There have been reports of scarcity of Barcelona both in the channel and among OEMs.

First Barcelona was delayed. When it came out, it was slow. Now we come to find out that issues delayed the ramp of the processor in high volume.

When asked what caused a delay in the volume ramp, the company responded that yields were not the issue.

Tuning Microprocessor Design to Process Technology

Rather the issue was tuning the microprocessor design of Barcelona to the 65-nm process technology AMD uses for the processor. Volume manufacturing required that the design of the CPU be better-tuned to the process manufacturing it is made on. “It is all a matter of wedding the design to the technology so as to be able to ship in volume”.

A Few Extra Weeks

The additional work required for turning on the high-volume ramp led to a delay of “a few extra weeks”.

Minor Issues

In wedding processor design with process technology in preparation for high volume, AMD experienced “minor issues”.

AMD Q3 2007 Earnings Call Transcript