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Xeon 7100 Family

September 14, 2K6

First there was Woodcrest and the Xeon 5100 family of processors. Then it was Montecito and the Itanium 2 9000 series. Most recently Intel announced the Xeon 7100 family of chips, codenamed Tulsa, for the high-end x86 multiprocessor (MP) server market.

This is why Intel calls this their summer of servers.

According to Intel, the Xeon 7100 chips offer as much as twice the performance of the previous multiprocessor server chips. That's nice. But what about the frontside bus (FSB)?

The FSB is a bottleneck, and the more processors you put on a board, the greater the bottleneck.

It's a process akin to sucking water through a straw when you're thirsty.

This isn't a weakness of the processor as much as it is a design of the system.

Intel hopes to counter the FSB with lots and lots of cache.

The L3 cache of the Xeon 7100 series is shared, much like the shared cache of the Core microarchitecture products (Core 2 Duo and Xeon 5100). However, it's an L3 cache, rather than L2.

The Xeon 7100 family of processors can scale to 32 dual-core processors. Beyond that, you will have to adopt Itanium 2 or scale out with additional x86 servers.

The new processor comes with a TDP rating of 95W, which isn't bad for NetBurst.

This will probably be the last series of chips based on the NetBurst microarchitecture.

The Xeon 7100 series appears to be the first x86 chip from Intel with over a billion transistors. Most of these transistors are located in the large cache. However, only the highest clocked Xeon 7100 processors have the full 16MB of L3 cache. Others have half that or less.

One thing about the new processors, though, is that they fit within existing Xeon 7000 systems. In other words, they are "socket compatible with the currently shipping platform".

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