The Core Microarchitecture

Background

Architectures and Microarchitectures

Intellectual Predecessor

The Energy Efficient Ideas

One of the mistakes that was made in the past was in equating performance with clock speed. "Contary to a popular misconception, it is not clock frequency (GHz) ... that equates to performance".

While clock speed does not equal performance, it is nevertheless very important to performance. Hence, the industry's continued fascination with clock speed, justifiably so, even after the gigahertz era has ended.

For clock speed remains one of the two most important determiners of performance, the other being the number of instructions that a processor executes at a time, or instructions per clock, IPC, for short.

The Core microarchitecture contains many features--new and old--that increase the number of instructions that its processors are able to execute at a time: such as Wide Dynamic Execution, Advanced Digital Media Boost, Micro-Ops Fusion, and Macro-Ops Fusion.

Wide Dynamic Execution is the ability of the processor to execute up to four instructions at a time, or per clock cycle. Previous generation microarchitectures (NetBurst and Mobile) were only able to execute up to three at a time.

Advanced Digital Media Boost gives a processor the ability to execute a whole 128-bit SSE (Streaming SIMD Extensions) instruction at a time, or per single clock cycle. Before it took two cycles to execute a single 128-bit SSE instruction. Now it takes one.

Micro-Ops Fusion is the ability to combine together separate instructions after they have been decoded and execute them as one. Core inherited Micro-Ops Fusion from the previous generation mobile microarchitecture.

Macro-Ops Fusion is the ability to combine separate instructions together into one before the instructions are decoded, as opposed to after they are decoded, as with Micro-Ops Fusion.

Wide Dynamic Execution, Advanced Digital Media Boost, Micro-Ops Fusion, and Macro-Ops Fusion are all technologies that enable processors of the Core microarchitecture to carry out more instructions per clock.

Instructions Per Clock

Power Consumption

Scalability

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