Core 2 Launch

Introduction

Core Microarchitecture

8/1 - The Core 2 processor family is based on the Core microarchitecture, which covers servers (Xeon 5100 series), desktops and notebooks (Core 2 Duo & Core 2 Extreme).

The earmarks of the Core microarchitecture are high performance, on the one hand, and energy efficiency, on the other.

The Core microarchitecture strives to do more work in less time.

Wide Dynamic Execution

One of the ways that Core accomplishes more in less time is by executing up to 4 instructions at a time, per clock cycle, whereas previous microarchitectures are able to execute at most three instructions at a time.

Advanced Digital Media Boost

Similarly, the Core microarchitecture can execute one full SSE (Streaming SIMD Extensions) instruction per clock, rather than taking more than one clock cycle to execute a SSE, like other designs.

Smart Memory Access

One of the advantages that AMD has over Intel is that AMD puts the memory controller on the CPU die, whereas with Intel the memory controller is part of the chipset. Using the northbridge of the chipset as a memory controller forces data to move along a front-side bus (FSB) on its way back and forth between the CPU and the northbridge.

The journey along the FSB increases the amount of time it takes the CPU to access data from memory, a factor known as latency, and the FSB also limits the amount of data to as much as can travel along the FSB. This is a memory bandwidth limitation.

AMD, on the other hand, is not limited in bandwidth by the FSB, because the FSB doesn't exist, and memory latencies are quite low because there is virtually no distance to travel to the memory controller, which is on the CPU die.

Intel addresses many of the shortcomings of a FSB architecture with Smart Memory Access.

Smart Memory Access makes the most of memory bandwidth traveling along the FSB. While the bandwidth of Core 2 processors is much improved over the previous generation Pentium D, this is one area in which AMD still commands a lead, thanks to its on-die memory controller.

The other issue that SMA addresses is latency. Intelligent prefetchers grab the data and have it ready for the CPU when the CPU needs it.

SMA hides the memory latency inherent in the front-side bus approach. It doesn't get rid of it. It's still there. Nevertheless, SMA works so well that Intel bests AMD on some latency benchmarks--in spite of AMD's on-die memory controller!

Active Smart Cache

The L2 cache under the Core microarchitecture is shared. This differs from the Pentium D, for instance, which has two independent, non-shared caches, one for each core. The problem is that, if data is present in one core's cache and needed by the other core, the other core takes a performance hit and has to go outside of the cache to retrieve the information.

However, not only is the L2 cache shared, it is dynamically allocated to the two cores in the most efficient manner. This way, a single core can use up to 100% of the shared cache, if the other core is idle. "Only Intel provides this capability in all segments".

New Processors

Desktop Processor Differences

Centrino Duo with the Core 2 Duo Processor

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