Woodcrest

6/25 - It's the eve of the big launch. Tomorrow, Intel is to launch its next generation Core microarchitecture, with the Xeon 5100 series.

The codename of the Xeon 5100 series is Woodcrest. It is the server counterpart of Core 2 Duo and Core 2 Extreme, and of Intel's new microarchitecture.

The server CPU uses a different socket from the Core 2 processor family. One uses 771 pins, the other 775. It's a different socket, but the same architecture.

Woodcrest succeeds Dempsey, on the Bensley and Glidewell platforms, for servers and workstations. You can fit a Woody onto a Dempsey board, and upgrade your Dempsey systems with Woodcrest.

Woodcrest does not clock as high, and lacks hyperthreading, yet somehow manages to outperform Dempsey by a large margin.

The performance benefits of Woodcrest make this one highly anticipated processor. Even Apple "is expected to be releasing Woodcrest based systems".

Woodcrest consumes alot less power than Dempsey, too. However, the memory that it uses--FB-DIMMs, or Fully Buffered DIMMs--requires more energy.

Woodcrest features a shared L2 cache, as with other Core microarchitecture products, such as Core 2 Duo and Extreme. The shared cache enables one core to fetch data that another core has pulled down, without having to go out over the frontside bus (FSB) to main memory, or beyond, to fetch the data.

Both Woodcrest and Clovertown are DP processors, meaning that they are designed for servers and workstations with up to 2 processors. They are not MP processors that can scale to 4 processors and beyond.

Clovertown is the quad-core equivalent of Woodcrest, but is not expected until the first of 2007. Before then, however, later this year, Intel is supposed to release a MP chip called Tulsa. Tulsa is not part of the Core microarchitecture, but will do MP.

The first Core microarchitecture MP chip appears to be Tigerton, on tap for 2007. Tigerton is to replace Intel's traditional frontside bus (FSB) with a different technology, which is good, because the FSB is currently the primary bottleneck. "The new technology gives each processor a direct pathway to the chipset".

Core 2 Solo

6/23 - When Intel announced the official names of its next generation mobile and desktop chips--Core 2 Duo and Core 2 Extreme--there was no mention of Core 2 Solo, causing many technical articles on the Internet to be rewritten.

As it turns out Core 2 Solo is alive and well, though we do not have its official name yet. The codename is Conroe-L, however. It's a single core Conroe. Conroe was the codename for what is now desktop Core 2 Duo and Core 2 Extreme.

Apparently there are substantial differences between the dual-core and single-core versions of the Core microarchitecture. Core 2 Duo appears to be closer akin to the server version of the Core microarchitecture than to single-core Conroe.

Core 2 Duo is even closer akin to the quad-core chips that Intel has on tap--Kentsfield, Clovertown, and Tigerton. Possibly because these quad-core chips are said to consists of two dual-core chips in a single package.

All of these dual-core and quad-core processors share the same processor signature, model, & stepping, whereas single-core Conroe does not. Single-core Conroe does belong to the same processor family, however. Consequently, 'Conroe-L is not part of the immediate Core 2 family processors, but part of an "extended family"'.

Maybe the reason for the differences in classification has something to do with the shared cache of the dual-core dice. With single-core, there's no shared L2 cache, because there's no second core to share the cache with.

With the dual-core chips, if one of the two cores is disabled, the other core can still make use of the full 4MB L2 cache: "if one core is disabled it does not mean half of the processor cache is disabled".

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